Zephyr

Zephyr · 35m

This is not true TSMC will introduce its version of Backside Power called Super Power Rail (SPR) with the A16 node, which will enter risk production soon. It's also more advanced than Intel's PowerVia, as TSMC directly connects the backside power to the transistors, while Intel's PowerVia uses nano TSVs to connect backside power to the transistors. Intel will transition to a similar architecture in 2028 with the 14A node called PowerDirect. TSMC isn't using High NA for 2-3 reasons. Multi-patterned Low-NA EUV will remain cheaper compared to High NA. The ecosystem around High NA is also not mature. TSMC doesn't want to commit a lot of CAPEX and waste cleanroom space to help mature it rn. Third, and most importantly, the reticle field size of High NA is half (26 x 16.5mm) compared to Low NA (26 x 33mm). So the size of the monolithic die that u can print in a single exposure is halved (429 mm² vs 858 mm²). So u need to use reticle stitching to print a larger monolithic die with High NA.

Zephyr · 1d

Very cool Matching the small Qwen with their first model release

Zephyr · 42m

What did I tell u, anon???

Zephyr · 19h

Well...